1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to an improvement technique for effectively taking advantage of an LDD (Lightly Doped Drain) structure.
2. Description of the Background Art
FIG. 29 is a front cross section showing a structure of a semiconductor device in the background art. A device 151 of this figure comprises a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and the MOSFET has an LDD (Lightly Doped Drain) structure. In this specification, according to the custom of this art, a transistor is referred to as MOSFET also when its gate electrode is not made of metal.
A semiconductor substrate 150 comprises a p-type well 61. A device isolation layer 64 is selectively buried in a major surface of the semiconductor substrate 150. Further, a pair of n+-type high-concentration semiconductor layers 62 and a shallower pair of nxe2x88x92-type low-concentration semiconductor layers 63 are selectively formed in a portion of the major surface of the semiconductor substrate 150 between the two device isolation layers 64. Respective ones of the paired low-concentration semiconductor layers 63 are formed as if extending off respective ones of the paired high-concentration semiconductor layers 62 towards a portion of the major surface between the paired high-concentration semiconductor layers 62.
In other words, the high-concentration semiconductor layers 62 and the low-concentration semiconductor layers 63 form an LDD structure. The high-concentration semiconductor layers 62 and the low-concentration semiconductor layers 63 correspond to source/drain regions of the MOSFET. An exposed surface layer of the well 61 between the paired high-concentration semiconductor layers 62 corresponds to a channel region CH of the MOSFET.
An insulating film 65 which is a silicon oxide film formed on the major surface of the semiconductor substrate 150, and a gate electrode 67 is so formed as to face the channel region CH on the insulating film 65. An insulating layer 68 is formed on the gate electrode 67. Sidewalls 70 are formed on the sides of the gate electrode 67 and the insulating layer 68.
An insulating layer 71 is so formed as to cover the above-described structure formed above the semiconductor substrate 150. In the insulating layer 71, a pair of contact holes 72 are selectively formed immediately above the pair of high-concentration semiconductor layers 62. Each of the contact holes 72 is filled with a conductive main electrode 73, and a pair of main electrodes 73 are thereby connected to the pair of high-concentration semiconductor layers 62, respectively. An interconnection layer 74 is placed on the insulating layer 71 to be connected to the main electrode 73.
Since the device 151 comprising the MOSFET has the above LDD structure, it is possible to relieve an electric field concentration that takes place in a pn junction between the well 61 and the semiconductor layers 62 and 63. As a result, a hot-carrier effect is suppressed and that increases the lifetime and reliability of the insulating film 65. Further, relieving the electric field concentration in the pn junction suppresses a leak current.
The background-art device 151, however, has a problem that the advantage of the LDD structure can not be fully taken in some cases due to the problematic manufacturing process. FIGS. 30 to 34 are process illustrations showing a method of manufacturing the device 151. The process begins with a step of FIG. 30.
In the step of FIG. 30, the semiconductor substrate 150 is prepared. In the major surface of the semiconductor substrate 150, the p-type well 61 is formed and the device isolation layer 64 is selectively buried therein. By thermal oxidation, the insulating film 76 is formed as a thermal oxide film on the major surface of the semiconductor substrate 150 and thereafter the gate electrode 67 and the insulating layer 68 are formed on the insulating film 76.
Next, as shown in FIG. 31, a pair of low-concentration semiconductor layers 63 are selectively formed. To form the low-concentration semiconductor layers 63, an n-type impurity is selectively implanted into the major surface of the semiconductor substrate 150 by using the gate electrode 67 and the insulating layer 68 as a mask and then diffused.
As shown in FIG. 32, the sidewalls 70 are formed of silicon oxide. A material of the sidewalls 70 is so deposited as to entirely cover an exposed surface above the semiconductor substrate 150 and then the deposited material is selectively removed by RIE (Reactive Ion Etching), to form the sidewalls 70 by such a self-alignment process. In this process, only a portion of the insulating film 76 covered with the gate electrode 67 and the sidewalls 70 is left as the insulating film 65.
After that, as shown in FIG. 33, a pair of high-concentration semiconductor layers 62 are selectively formed in the major surface of the semiconductor substrate 150. To form the high-concentration semiconductor layers 62, an n-type impurity is selectively implanted into the major surface of the semiconductor substrate 150 by using the gate electrode 67, the insulating layer 68 and the sidewalls 70 as a mask and then diffused.
Next, a step of FIG. 34 is executed. In the step of FIG. 34, a material of the insulating layer 71 is so deposited as to entirely cover an exposed surface above the semiconductor substrate 150. After that, contact holes 72 are formed in the deposited material. Referring back to FIG. 29, the contact holes 72 are each filled with a conductive material, to form the main electrodes 73. The interconnection layer 74 is so placed on the insulating layer 71 as to be connected to the main electrode 73. Through the above steps, the device 151 is completed.
Among the above manufacturing process steps, the step of FIG. 32 for forming the sidewalls 70 causes the problem of losing advantage of the LDD structure. This is illustrated in FIG. 35. As shown in FIG. 35, the major surface of the semiconductor substrate 150 is also etched in some cases in a step of anisotropic etching using RIE.
This is caused by forming the insulating film 65 with thickness of only about 7 to 8 nm when the gate electrode 67 has a width of e.g., 0.15 xcexcm, which is a typical value, (along the channel length, i.e., from one of the paired low-concentration semiconductor layers 63 to the other). When the major surface of the semiconductor substrate 150 is etched, as indicated by the sign xe2x80x9cAxe2x80x9d of FIG. 35, the edge of the high-concentration semiconductor layer 62 is not fully covered with the low-concentration semiconductor layer 63. As a result, an electric field concentration occurs in the pn junction represented by the sign xe2x80x9cAxe2x80x9d and the hot-carrier effect is increased. Further, the electric field concentration in the pn junction increases a leak current. As a result, the advantage of using the LDD structure is reduced.
With size reduction of devices, the source/drain region of the MOSFET becomes shallower. Therefore, as devices are downsized more and more, the ill effect of etching damage on the semiconductor substrate 150 in formation of the sidewalls becomes more pronounced.
The present invention is directed to a semiconductor device. According to a first aspect of the present invention, the semiconductor device comprises: a semiconductor substrate comprising a major surface of a first conductivity type, a pair of low-concentration semiconductor layers of a second conductivity type selectively formed in the major surface separately from each other and a pair of high-concentration semiconductor layers of the second conductivity type selectively formed in the major surface separately from each other, having opposed edges recessed from opposed edges of the pair of low-concentration semiconductor layers, being deeper and higher in concentration than the pair of low-concentration semiconductor layers; a first insulating film formed immediately on the major surface; a gate electrode so formed on the first insulating film as to face a region between the opposed edges of the pair of low-concentration semiconductor layers; a pair of main electrodes connected to the pair of high-concentration semiconductor layers respectively; sidewalls being insulative and covering sides of the gate electrode and a portion of the first insulating film adjacent to the gate electrode; and a second insulating film whose main component is different from that of the sidewalls, covering a surface of the gate electrode except a portion facing the first insulating film so as to isolate the gate electrode from the sidewalls and covering an upper portion of the first insulating film not facing the gate electrode so as to insolate the first insulating film from the sidewalls and not as to extend off the sidewalls.
According to a second aspect of the present invention, the semiconductor device of the first aspect further comprises: a third insulating film whose main component is different from that of the second insulating film, covering the surface of the gate electrode except the portion facing the first insulating film so as to isolate the gate electrode from the second insulating film, isolating the first insulating film from the second insulating film and covering the upper portion of the first insulating film not facing the gate electrode.
According to a third aspect of the present invention, the semiconductor device of the second aspect further comprises: an insulating layer formed above the major surface and selectively defining a pair of contact holes which the pair of main electrodes penetrate respectively, and in the device of the third aspect, the first insulating film, the third insulating film and the insulating layer include the same main component.
Preferably, the semiconductor substrate includes silicon as its main component, the sidewalls, the first insulating film, the third insulating film and the insulating layer include silicon oxide as their main component, and the second insulating film includes silicon nitride as its main component.
According to a fourth aspect of the present invention, the semiconductor device comprises: a semiconductor substrate comprising a major surface of a first conductivity type, a pair of low-concentration semiconductor layers of a second conductivity type selectively formed in the major surface separately from each other and a pair of high-concentration semiconductor layers of the second conductivity type selectively formed in the major surface separately from each other, having opposed edges recessed from opposed edges of the pair of low-concentration semiconductor layers, being deeper and higher in concentration than the pair of low-concentration semiconductor layers; a first insulating film formed immediately on the major surface; a gate electrode so formed on the first insulating film as to face a region between the opposed edges of the pair of low-concentration semiconductor layers; a pair of main electrodes connected to the pair of high-concentration semiconductor layers respectively; sidewalls being insulative and covering sides of the gate electrode and a portion of the first insulating film adjacent to the gate electrode; a second insulating film interposed between the sidewalls and the gate electrode; and a third insulating film whose main component is different from that of the sidewalls, interposed between the sidewalls and the first insulating film.
According to a fifth aspect of the present invention, the semiconductor device of the fourth aspect further comprises: an insulating layer formed above the major surface and selectively defining a pair of contact holes which the pair of main electrodes penetrate respectively, and in the device of the fifth aspect, the first insulating film, the third insulating film and the insulating layer include the same main component.
Preferably, the semiconductor substrate includes silicon as its main component, the first insulating film, the third insulating film and the insulating layer include silicon oxide as their main component, and the second insulating film includes a layer including silicon oxide as its main component at least on a side not facing the gate electrode.
Preferably, the semiconductor substrate includes silicon as its main component, the first insulating film, the third insulating film and the insulating layer include silicon oxide as their main component, and the second insulating film includes a layer including silicon nitride as its main component at least on a side facing the gate electrode.
According to a sixth aspect of the present invention, the semiconductor device of the fourth aspect further comprises: a first insulating layer formed on the gate electrode; and a second insulating layer whose main component is different from that of the sidewalls and said first insulating film, formed above the major surface and selectively defining a pair of contact holes which the pair of main electrodes penetrate respectively.
Preferably, the pair of contact holes are formed with spacing narrower than the width of the gate electrode along a direction from one of the pair of low-concentration semiconductor layers to the other.
The present invention is also directed to a method of manufacturing a semiconductor device. According to a seventh aspect of the present invention, the method comprises the steps of: (a) preparing a semiconductor substrate having a major surface of a first conductivity type; (b) forming a first insulating film on the major surface; (c) forming a gate electrode on the first insulating film; (d) selectively introducing an impurity into the major surface with the gate electrode as a mask to selectively form a pair of low-concentration semiconductor layers in the major surface, being separated from each other with at least a portion of a region immediately below the gate electrode interposed therebetween; (e) forming a second insulating film for covering the gate electrode and the first insulating film at least after the step (c); (f) depositing a material whose main component is different from that of the second insulating film so as to entirely cover an exposed surface above the major surface after the steps (d) and (e); (g) anisotropically etching the material deposited in the step (f) to form sidewalls for covering sides of the gate electrode and a portion of the first insulating film adjacent to the gate electrode; (h) performing a selective etching to selectively remove a portion of the second insulating film existing along the first insulating film and uncovered by the sidewalls; (i) selectively introducing an impurity into the major surface with the gate electrode, the second insulating film and the sidewalls as a mask to selectively form a pair of high-concentration semiconductor layers of a second conductivity type having opposed edges recessed from opposed edges of the pair of low-concentration semiconductor layers, being deeper and higher in concentration than the pair of low-concentration semiconductor layers, in the major surface at least after the step (g); and (j) connecting a pair of main electrodes to the pair of high-concentration semiconductor layers respectively.
According to an eighth aspect of the present invention, the method of the seventh aspect further comprises the step of: (k) forming a third insulating film for covering the gate electrode and the first insulating film by using a material whose main component is different from that of the second insulating film after the step (c) before the step (e).
According to a ninth aspect of the present invention, in the method of the eighth aspect, the third insulating film formed in the step (k) has the same main component as the first insulating film, and the step (j) comprises the steps of: (j-1) depositing a material whose main component is the same as that of the first insulating film entirely on an exposed surface above the major surface to form an insulating layer; (j-2) selectively etching the insulating layer to selectively form a pair of contact holes in portions immediately above a region including a portion of the pair of high-concentration semiconductor layers; and (j-3) filling the pair of contract holes with an electrode material to form the pair of main electrodes.
Preferably, the semiconductor substrate prepared in the step (a) includes silicon as its main component, the first insulating film formed in the step (b), the material deposited in the step (f), the third insulating film formed in the step (k) and the insulating layer formed in the step (j-1) are each include silicon oxide as their main component, and the second insulating film formed in the step (e) includes silicon nitride as its main component.
According to a tenth aspect of the present invention, the method comprises the steps of: (a) preparing a semiconductor substrate having a major surface of a first conductivity type; (b) forming a first insulating film on the major surface; (c) forming a gate electrode on the first insulating film; (d) selectively introducing an impurity into the major surface with the gate electrode as a mask to selectively form a pair of low-concentration semiconductor layers in the major surface, being separated from each other with at least a portion of a region immediately below the gate electrode interposed therebetween; (e) forming a second insulating film on a side surface of the gate electrode at least after the step (c); (f) forming a third insulating film whose main component is different from that of the first insulating film on a portion of the first insulating film uncovered with the gate electrode after the step (e); (g) depositing a material whose main component is different from that of the third insulating film so as to entirely cover an exposed surface above the major surface after the step (f); (h) anisotropically etching the material deposited in the step (g) to form sidewalls for covering sides of the gate electrode and a portion of the first insulating film adjacent to the gate electrode; (i) selectively introducing an impurity into the major surface with the gate electrode and the sidewalls as a mask to selectively form a pair of high-concentration semiconductor layers of a second conductivity type having opposed edges recessed from opposed edges of the pair of low-concentration semiconductor layers, being deeper and higher in concentration than the pair of low-concentration semiconductor layers, in the major surface; and (j) connecting a pair of main electrodes to the pair of high-concentration semiconductor layers respectively.
According to an eleventh aspect of the present invention, in the method of the tenth aspect, the third insulating film formed in the step (f) has the same main component as the first insulating film, and the step (j) comprises the steps of: (j-1) depositing a material whose main component is the same as that of the first insulating film entirely on an exposed surface above the major surface to form an insulating layer; (j-2) selectively etching the insulating layer to selectively form a pair of contact holes in portions immediately above a region including a portion of the pair of high-concentration semiconductor layers; and (j-3) filling the pair of contract holes with an electrode material to form the pair of main electrodes.
Preferably, the semiconductor substrate prepared in the step (a) includes silicon as its main component, the second insulating film formed in said step (e) includes silicon nitride as its main component, and the first insulating film formed in the step (b), the third insulating film formed in the step (f) and the insulating layer formed in the step (j-1) each include silicon oxide as their main component.
Preferably, the third insulating film is formed by thermal oxidation in the step (f).
Preferably, the thermal oxidation is so executed as to leave a layer which includes silicon oxide as its main component in the second insulating film in the step (f).
According to a twelfth aspect of the present invention, the method of the tenth aspect further comprises the step of: (k) forming a first insulating layer on the gate electrode at least before the step (g), and in the method of the twelfth aspect, the step (j) comprises the steps of: (j-1) depositing a material whose main component is different from those of the material deposited in the step (g) and the first insulating layer entirely on an exposed surface above the major surface to form a second insulating layer; (j-2) selectively etching the second insulating layer to selectively form a pair of contact holes in portions immediately above a region including a portion of the pair of high-concentration semiconductor layers; and (j-3) filling the pair of contract holes with an electrode material to form the pair of main electrodes.
Preferably, the pair of contact holes are formed with spacing narrower than the width of the gate electrode along a direction from one of the pair of low-concentration semiconductor layers to the other in the step (j-2).
Since the second insulating film is provided as an underlying layer of the sidewalls in the device of the first aspect, the second insulating film serves as a protective film for the major surface of the semiconductor substrate in the step of performing a selective etching to form the sidewalls in the process for manufacturing the device. This relieves an electric field concentration in a pn junction and the intrinsic advantage of the LDD structure can be effectively taken. Further, since the portion of the second insulating film covering the first insulating film does not extend off the sidewalls, there is no need for removing the second insulating film by etching. Therefore, the main electrodes can be formed with spacing narrower than the width of the gate electrode while the second insulating film prevents a short circuit between the main electrodes and the gate electrode.
Since the third insulating film is provided in the device of the second aspect, it becomes possible to remove the second insulating film without damaging the major surface of the semiconductor substrate in the process for manufacturing the device.
Since the first insulating film, the third insulating film and the insulating layer include the same component as their main component in the device of the third aspect, it is easy to form the contact hole which penetrates the insulating layer.
Since the third insulating film is provided as an underlying layer of the sidewalls in the device of the fourth aspect, the third insulating film serves as a protective film for the major surface of the semiconductor substrate in the step of performing a selective etching to form the sidewalls in the process for manufacturing the device. This relieves an electric field concentration in a pn junction and the intrinsic advantage of the LDD structure can be effectively taken. Further, since the second insulating film is interposed between the sidewalls and the gate electrode, the second insulating film serves as a protective film for the gate electrode in the step of forming the third insulating film before forming the sidewalls. That suppresses thinning of the gate electrode.
Since the first insulating film, the third insulating film and the insulating layer include the same component as their main component in the device of the fifth aspect, it is easy to form the contact hole which penetrates the insulating layer.
In the device of the sixth aspect, a pair of main electrodes are connected to a pair of high-concentration semiconductor layers through the contact holes formed in the second insulating layer whose main component is different from that of the sidewalls and the first insulating layer. Therefore, the contact holes are formed by etching only the second insulating layer with less effect on the sidewalls and the first insulating layer. It is thereby possible to form a pair of contact holes at such a position as to overlap the gate electrode and prevent a short circuit between the main electrodes and the gate electrode even with low accuracy of mask-pattern alignment. Further, it becomes possible to form a pair of main electrodes with spacing narrower than the width of the gate electrode. This facilitates size reduction of the device.
Since the material of the sidewall is deposited on the second insulating film and then selectively etched to form the sidewalls in the manufacturing method of the seventh aspect, the second insulating film serves as a protective film for the major surface of the semiconductor substrate. This relieves an electric field concentration in a pn junction and the intrinsic advantage of the LDD structure can be effectively taken. Further, since the portion of the second insulating film covering the first insulating film is so removed as not to extend off the sidewalls, there is no need for removing the second insulating film by etching when the sidewalls are formed. Therefore, the main electrodes can be formed with spacing narrower than the width of the gate electrode while the second insulating film prevents a short circuit between the main electrodes and the gate electrode.
Since the third insulating film is provided as an underlying layer of the second insulating film in the manufacturing method of the eighth aspect, it becomes possible to remove the second insulating film without damaging the major surface of the semiconductor substrate.
Since the first insulating film, the third insulating film and the insulating layer include the same component as their main component in the manufacturing method of the ninth aspect, it is easy to form the contact hole which penetrates the insulating layer.
Since the material of the sidewall is deposited on the third insulating film and then selectively etched to form the sidewalls in the manufacturing method of the tenth aspect, the third insulating film serves as a protective film for the major surface of the semiconductor substrate. This relieves an electric field concentration in a pn junction and the intrinsic advantage of the LDD structure can be effectively taken. Further, since the second insulating film is formed on the side surface of the gate electrode before forming the third insulating film, the second insulating film serves as a protective film for the gate electrode. That suppresses thinning of the gate electrode.
Since the first insulating film, the third insulating film and the insulating layer include the same component in the manufacturing method of the eleventh aspect, it is easy to form the contact hole which penetrates the insulating layer.
In the manufacturing method of the twelfth aspect, a pair of contact holes to be filled with a pair of main electrodes are formed in the second insulating layer whose main component is different from that of the sidewalls and the first insulating layer. Therefore, the contact holes are formed by etching only the second insulating layer with less effect on the sidewalls and the first insulating layer. It is thereby possible to form a pair of contact holes at such a position as to overlap the gate electrode and prevent a short circuit between the main electrodes and the gate electrode even with low accuracy of mask-pattern alignment. Further, it becomes possible to form a pair of main electrodes with spacing narrower than the width of the gate electrode. This facilitates size reduction of the device.
An object of the present invention is to provide a semiconductor device which suppresses an electric field concentration in a pn junction without losing the advantage of an LDD structure and can thereby effectively suppress a hot-carrier effect and a leak current, and provide a method of manufacturing the semiconductor device.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.